Through the openings in the isolating layer, interconnections are formed between the two patterns of conductors. The first pattern, which is provided on the surface of the semiconductor body, is locally in contact with semiconductor regions. Through interconnections these semiconductor regions are connected to the second pattern of conductors. Since the interconnections are formed at areas located both above a semicondutor region and above an adjoining isolation region, much space is saved on the surface of the semiconductor body. In practice, openings in the isolating layer, through which the interconnections are established, have dimensions which are determined by the manufacturing process comprising lithographic and etching processing steps. For example, such an opening has a cross-section of 1.times.1 .mu.m. If the interconnections are formed at areas located only above semiconductor regions, these semiconductor regions must have dimensions which are larger than those of the openings in the isolating layer If the interconnections are formed at areas located both above a semiconductor region and above an adjoining isolation region, the openings are consequently present only in part above the semiconductor regions so that these semiconductor regions can be considerably smaller. In the first case, the semiconductor regions must have, for example, a surface area of about 2.times.2 .mu.m, while in the second case they can have a considerably smaller surface area.
From the article "A New Device Interconnect Scheme for Submicron VLSI" by D. C. Chen et al. Technical Digest of the International Electron Devices Meeting, 1984, p. 118-121, a method is known of the kind mentioned in the opening paragraph, in which the mutual contacts are present at areas which are located both above semiconductor region and above a field isolation region. These contacts between the first and second patterns of conductors are established by etching into the isolating layers windows terminating on the first pattern of conductors and by providing the second pattern of conductors over the windows thus formed.
In the known method, in which both the isolating layer and the field isolation regions consist of silicon oxide, the first pattern of conductors serves as an etching stopper when etching the window. As a result, the yield oxide is protected during etching at the areas at which the window is formed. If this should not be the case, after etching the window into the isolating layer of silicon oxide, the field oxide is also etched. If the etching process is not stopped in time, the field oxide can locally be etched away entirely. After the second pattern of conductors has been provided, a pn junction terminating on the field oxide would be shortcircuited. Especially in those cases in which the pn junction extends comparatively closely to the surface of the semiconductor body, it is difficult to stop the etching process in time. This is certainly the case in semiconductor devices in which semiconductor regions, field isolation regions, conductors and contact windows having dimensions in the micron and the submicron range must be realized.
In the known method described, the first pattern of conductors serves as an etching stopper when etching the windows into the isolating layer. At the area of each window, for this purpose a part of the first pattern should be present having a surface area larger than the surface area of the cross-section of the window. In order to prevent the undesired etching of the field isolation region described above, this surface area must be at least so large that, when the window is formed, the etching stopper is present under all circumstances when etching the window. The window is defined by a photolithographic mask which is imaged on a layer of photoresist provided on the surface of the semiconductor body. After development, an opening of, for example, 1.times.1 .mu.m is formed in the photoresist. Subsequently, the window is etched while using the remaining photoresist as a mask. Since the photolithographic mask is imaged with a given alignment tolerance (of about .+-.0.3 .mu.m), the window mostly does not exactly arrive at its place. It is only certain that it arrives at an area which is as large as the mask extended with an edge equal to the alignment tolerance. In the embodiment with a window of 1.times.1 .mu.m, this is consequently an area of 1.6.times.1.6 .mu.m. If the part of the first pattern of conductors serving as an etching stopper when forming the window is provided by a similar photolithographic method, in which similar tolerances play a part, this part must have a surface area as large as the area at which the window is formed plus a strip having a width equal to the alignment tolerance. In the embodiment, this is consequently a square of 2.2.times.2.2 .mu.m. This requires on the surface a space which is again larger by the same amount. In the embodiment, this is consequently 2.8.times.2.8 .mu.m. For a window of 1.times.1 .mu.m, an etching stopper of 2.2.times.2.2 .mu.m must therefore be present, for which purpose a space of 2.8.times.2.8 .mu.m must be reserved on the surface of the semiconductor body.